Semiconductor device modelling
TCAD, MOS structures, transport, traps, interface effects, and model-to-measurement calibration.
nm → μmI am Dilip Khanal, a mechanical engineering graduate building a computational research path across semiconductor devices, materials, and hardware reliability. My work starts with physical models and earns its confidence through experimental validation.
My background is not a conventional straight line into nanoelectronics. That is useful when the problem crosses device physics, mechanics, heat transfer, materials, and manufacturing.
TCAD, MOS structures, transport, traps, interface effects, and model-to-measurement calibration.
nm → μmFinite-element thinking, structure–property relationships, nanocomposites, fabrication, and characterization.
μm → mmHeat transfer, CFD, thermo-mechanical reliability, scientific computing, and electronics thermal management.
mm → packageThese projects show the progression from fabrication and characterization toward physics-based simulation and experimentally grounded modelling.
At National Taiwan University, I built and calibrated Silvaco Victory Device models against measured C–V and Gp/ω data. The study showed that distributed bulk traps reproduced the observed frequency dispersion more convincingly than an interface-only explanation.
I worked across material preparation, SLA fabrication, mechanical and electrical testing, and characterization. Higher conductivity came with a real trade-off: graphene agglomeration reduced tensile and impact performance.
I prepared seeded substrates, grew ZnO nanowires, and used FESEM and EDAX for characterization. Sparse nanowire coverage and substrate-dominated signals exposed the gap between a synthesis result and a reliable device.
Book chapter in Proceedings in Materials, developed from work presented orally at ASMP 2024, IIT Madras.
Oral conference contribution; device-modelling and manuscript-preparation role.
Presented model calibration and interpretation during the TEEP research visit.
A mechanical foundation, hands-on materials work, and a deliberate move into semiconductor modelling.
TEEP-funded research at the Graduate Institute of Photonics and Optoelectronics, focused on experimentally calibrated semiconductor TCAD.
First Class, CGPA 7.03/10; final-semester SGPA 9.4/10. The degree was taught entirely in English.
Presented graphene–PUA nanocomposite research spanning additive manufacturing, mechanical response, and electrical performance.
Seeking rigorous work in computational engineering, semiconductor devices, multiphysics, thermal transport, or hardware reliability—with a credible path from equations to validation.
Samsung Fellowship, IISc Semiconductor Workforce Development Program, 2025
CeNSE Summer School, Indian Institute of Science
ESSCI / NSQF Level 6 Foundation Program in Nano Science and Technology
Indian Council for Cultural Relations scholarship, 2021–2025
For research opportunities, graduate supervision, or technical collaboration, contact me directly.